pdu1 7f doc #97005 data delay devices, inc. 1 1/14/97 3 mt. prospect ave. clifton, nj 07013 7-bit programmable delay line (series pdu17f) features packages digitally programmable in 128 delay steps monotonic delay-versus-address variation two separate outputs: inverting & non-inverting precise and stable delays input & outputs fully ttl interfaced & buffered 10 t 2 l fan-out capability fits standard 40-pin dip socket auto- insertable functional description the pdu17f-series device is a 7-bit digitally programmable delay line. the delay, td a , from the input pin (in) to the output pins (out, out/) depends on the address code (a6-a0) according to the following formula: td a = td 0 + t inc * a where a is the address code, t inc is the incremental delay of the device, and td 0 is the inherent delay of the device. the incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. the enable pins (en/) are held low during normal operation. these pins must always be in the same state and may be tied together externally. when these signals are brought high, out and out/ are forced into low and high states, respectively. the address is not latched and must remain asserted during normal operation. series specifications programmed delay tolerance: 5% or 2ns, whichever is greater inherent delay (td 0 ): 13ns typical (out) 12ns typical (out/) setup time and propagation delay: address to input setup (t ais ): 10ns disable to output delay (t diso ): 6ns typ. (out) operating temperature: 0 to 70 c temperature coefficient: 100ppm/ c (excludes td 0 ) supply voltage v cc : 5vdc 5% supply current: i cch = 68ma i ccl = 86ma minimum pulse width: 8% of total delay 1997 data delay devices data delay devices, inc. 3 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 n/c out/ out en/ gnd n/c n/c n/c gnd n/c n/c n/c n/c gnd n/c en/ n/c in n/c gnd vcc n/c a0 a1 a2 vcc n/c a3 a4 a5 vcc n/c n/c n/c n/c vcc n/c a6 n/c n/c pdu17f-xx dip pdu17f-xxc5 gull-wing pdu17f-xxm military dip pdu17f-xxmc5 military gull-wing pin descriptions in delay line input out non-inverted output out/ inverted output a0-a6 address bits en/ output enable vcc +5 volts gnd ground dash number specifications part number incremental delay per step ( ns) total delay change ( ns) pdu17f-.5 .5 .3 63.5 3.2 pdu17f-1 1 .5 127 6.4 pdu17f-2 2 .5 254 12.7 pdu17f-3 3 1.0 381 19.1 pdu17f-4 4 1.0 508 25.4 pdu17f-5 5 1.5 635 31.8 pdu17f-6 6 1.5 762 38.1 pdu17f-8 8 2.0 1,016 50.8 pdu17f-10 10 2.0 1,270 63.5 note: any dash number between .5 and 10 not shown is also available.
pdu17f doc #97005 data delay devices, inc. 2 1/14/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes address update the pdu17f is a memory device. as such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. the timing restrictions are shown in figure 1. after the last signal edge to be delayed has appeared on the out pin, a minimum time, t oax , is required before the address lines can change. this time is given by the following relation: t oax = max { (a i - a i-1 ) * t inc , 0 } where a i-1 and a i are the old and new address codes, respectively. violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t oax has elapsed. a similar situation occurs when using the en/ signal to disable the output while in is active. in this case, the unit must be held in the disabled state until the device is able to ?clear? itself. this is achieved by holding the en/ signal high and the in signal low for a time given by: t dish = a i * t inc violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the out pin. the possibility of spurious signals persists until the required t dish has elapsed. input restrictions there are three types of restrictions on input pulse width and period listed in the ac characteristics table. the recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. the suggested conditions are those for which signals will propagate through the unit without significant distortion. the absolute conditions are those for which the unit will produce some type of output for a given input. when operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. however, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. in other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. please consult the technical staff at data delay devices if your application has specific high-frequency requirements. please note that the increment tolerances listed represent a design goal. although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. monotonicity is, however, guaranteed over all addresses. t diso t oax t aens t enis pw in td a pw out t dish a6-a0 en/ in out out/ figure 1: timing diagram a i-1 a i t skew t ais
pdu1 7f doc #97005 data delay devices, inc. 3 1/14/97 3 mt. prospect ave. clifton, nj 07013 device specifications table 1: ac characteristics parameter symbol min typ units total programmable delay td t 127 t inc inherent delay td 0 13.0 ns output skew t skew 1.5 ns disable to output low delay t diso 6.0 ns address to enable setup time t aens 2.0 ns address to input setup time t ais 10.0 ns enable to input setup time t enis 8.0 ns output to address change t oax see text disable hold time t dish see text absolute per in 16 % of td t input period suggested per in 32 % of td t recommended per in 200 % of td t absolute pw in 8 % of td t input pulse width suggested pw in 16 % of td t recommended pw in 100 % of td t table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v cc -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min typ max units notes high level output voltage v oh 2.5 3.4 v v cc = min, i oh = max v ih = min, v il = max low level output voltage v ol 0.35 0.5 v v cc = min, i ol = max v ih = min, v il = max high level output current i oh -1.0 ma low level output current i ol 20.0 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input clamp voltage v ik -1.2 v v cc = min, i i = i ik input current at maximum input voltage i ihh 0.1 ma v cc = max, v i = 7.0v high level input current i ih 20 m a v cc = max, v i = 2.7v low level input current i i l -0.6 ma v cc = max, v i = 0.5v short-circuit output current i os -60 -150 ma v cc = max output high fan-out 25 unit output low fan-out 12.5 load
pdu17f doc #97005 data delay devices, inc. 4 1/14/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com package dimensions 2.100 max. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 .280 max. .015 typ. .070 max. .018 typ. .580 max. .650 max. .010 .002 lead material: nickel-iron alloy 42 tin plate 20 19 18 17 24 23 22 21 29 30 31 32 33 34 35 25 26 27 28 36 37 38 39 40 .100 typ. dip (pdu17f-xx, pdu17f-xxm) 2.080 .020 .882 .005 .020 typ. .040 typ. .100 .090 1.100 .280 max. .590 max. .010 .002 .050 .010 .710 .005 .007 .005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 gull-wing (pdu17f-xxc5, pdu17f-xxmc5)
pdu1 7f doc #97005 data delay devices, inc. 5 1/14/97 3 mt. prospect ave. clifton, nj 07013 delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 1 fast-ttl gate supply voltage ( vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.5 x total delay period: per in = 4.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out out trig in ref trig test setup device under test (dut) time interval counter pulse generator computer system printer in timing diagram for testing td ar td af per in pw in t rise t fall 0.6v 0.6v 1.5v 1.5v 2.4v 2.4v 1.5v 1.5v v ih v il v oh v ol input signal output signal
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